1. Field of the Invention
The present invention relates to the field of planarization, and more specifically, to ceria based abrasives for chemical-mechanical polishing (CMP).
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These electrically conductive structures are often referred to as contacts or vias.
A consequence of having multiple layers of patterned conductive material separated by an insulating layer is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant. Recently, polymers have been introduced for use in integrated circuit manufacturing as dielectrics having a lower dielectric constant than conventionally used oxides of silicon.
Nonplanar surfaces, when present in integrated circuits having complex, high density multilevel interconnections, may cause the optical resolution of photolithographic processing steps to be poor, which could inhibit the printing of high density lines. Another problem that may be caused by nonplanar surface topography relates to step coverage of metal layers. If steps are too high or uneven, open circuits could be created. It is thus important, when making such complex integrated circuits, to planarize the surface of many of the layers that make up the device.
Various techniques have been developed to planarize certain layers formed during the process of making integrated circuits. In one approach, known as chemical-mechanical polishing, protruding steps, such as those that may be formed along the upper surface of interlayer dielectrics (xe2x80x9cILDsxe2x80x9d), are removed by polishing. Chemical-mechanical polishing may also be used to planarize conformally deposited metal layers to form planar plugs or vias.
Accordingly, there is a need for CMP methods and apparatus to polish low dielectric constant materials such as polymers.
Briefly, a ceria based slurry is used in a chemical mechanical polishing operation at low polish pressure, and a predetermined pH range, to achieve high polish rates and good uniformity when planarizing films formed from low dielectric constant materials, such as polymers.
In a further aspect of the present invention, the distribution of ceria particle sizes in a slurry is bimodal, that is, controlled such that there are two distinct particle size ranges.
In a particular, exemplary embodiment of the present invention, a ceria based polishing slurry containing a bimodal distribution of ceria particle sizes is used in a CMP polisher apparatus with a polishing pressure of approximately 3 psi and a pH of approximately 10.6 to planarize fluorinated organic polymers.